Mutually phase-shifted control signals are frequently needed in engineering applications. For the generation of periodic, mutually phase-shifted control signals, it is important that the phase relationship between the control signals be well-defined. In practice, this mostly means that control signals must be synchronous; i.e., the control signals have the same period duration, or at least period durations which are integral multiples of each other.
One application where high-accuracy control signals are required is in microscopes, in particular confocal microscopes, such as STED and FLIM microscopes. There, two or more phase-shifted synchronous control signals are needed to control the illumination laser and, if applicable, the detection device.
Stimulated emission depletion (STED) microscopes achieve resolutions beyond the limit that is theoretically achievable by optical microscopes; i.e., it is possible to resolve structures smaller than λ/2 of the illuminating light. In order to achieve this, one makes use of the effect that illumination of a fluorescing sample with a wavelength near the fluorescence wavelength causes the sample to change from an excited state to a de-excited state. In a STED microscope, a fluorescent sample is initially excited by a short wavelength laser beam, and subsequently de-excited by a long wavelength laser beam, the long wavelength laser beam having a ring-shaped intensity distribution which is nearly zero in the center. In this way, it is possible to achieve resolutions down to 30 nm and below. In order to achieve resolutions as high as this, it is essential to control the timing of the lasers as accurately as possible.
This applies similarly to fluorescence lifetime imaging (FLIM) microscopes, which measure the “lifetime” of an excited state of a fluorescent molecule. In FLIM with PIE (Pulse Interleaved Excitation), the sample is alternately excited by lasers having different wavelengths. There, too, the laser must be controlled such that they have a well-defined temporal relationship to each other.
A circuit for generating such control signals, as is known in the art, is schematically shown in FIG. 1. A clock signal CLK is applied to a pulse generator A, which is often implemented as an up counter. When a comparison value B stored in a register C is reached, a pulse having the width of an active level of clock signal CLK is provided at output D of pulse generator A and the counter is reset. The pulse train provided at output D and an additional signal generated from this pulse train by a clock divider are transmitted to a circuit E, which generates and outputs the control signals. Circuit E is substantially formed by a multiplexer and a digital logic circuit and is adjustable within certain limits by a configuration F. Depending on configuration F, control signals PULSE_OUT1 through n are provided at the outputs of circuit E. Mostly, mutually phase-shifted signals are needed only at two of the outputs.
In order to facilitate the understanding of the underlying principle, FIG. 2 shows a greatly simplified example of different pulse trains. FIG. 2A shows a pulse train as is output by pulse generator A at output D. For the sake of simplicity, the pulse train is assumed to be identical to the applied clock signal CLK. This can be achieved by storing in register C a comparison value equal to 1. Thus, at each clock edge, the counter reaches the comparison value, whereupon a pulse is generated and the counter is reset. The pulse train has a period duration T, and each of the active levels of the pulse train has a width tA.
Circuit E generates from this pulse train the pulse trains shown in FIGS. 2B and 2C; the pulse train of FIG. 2C being phase-shifted by 180° with respect to the pulse train of FIG. 2B.
This prior art circuit has the disadvantage of providing little flexibility. Apart from some minor configuration options, the definition of circuit E determines the output signals of the circuit. It is not possible to generate output signals other than those determined in this way. Any changes beyond the available configuration options require circuit E to be significantly modified.